Today, integrated circuits contain millions of transistors on a single chip, with many critical circuit features having measurements in the deep sub-micron range. As manufacturers implemented more and more circuit elements in smaller and smaller silicon substrate surface areas, engineers and designers developed hardware and software tools to automate much of the integrated circuit design and manufacturing process. While these software and hardware tools have drastically reduced the time from conception to production, these same tools currently have manufacturing limitations. One such limitation is reliability of the integrated circuits, both during manufacturing and testing stages, and in the final product chips. As they are currently being used, these tools also interfere with increasing circuit component densities.
While there are several approaches to developing integrated circuits, a primary method today uses standard cells in the development process. This standard cell method, also referred to as cell-based topology, has the advantage of achieving greater circuit densities than other methods, such as a gate array method. Like the gate array method, standard cell designs rely on a set of predefined circuit elements, called cells, to implement the circuit design. The complexity of standard cells can range from simple logic gates, such as those found in gate arrays, to block-level components such as RAMs, ROMs, and PLAs. In other words, the cell-based topology may comprise low-level cells, such as n-fet and p-fet transistors, or it may comprise complex function blocks, designed either from scratch or by combining lower-level cells.
Designers and engineers commonly design and fabricate semiconductor integrated circuits by first preparing a schematic diagram or hardware description language (HDL) specification of a logical circuit. The HDL specification provides the details for how the circuit elements are interconnected. With standard cell technology, the schematic diagram or HDL specification is synthesized into standard cells of a specific cell library. Each standard cell corresponds to a logical function that is implemented using transistors.
Using the HDL specification and standard cells from a cell library, the particular interconnections of the circuit elements of an integrated circuit design are typically expressed as a list of network elements, a.k.a. a net list. A series of computer-aided design tools generate this net list of standard cells and the interconnections between the cells. A floor planner or placement tool uses the net list to place the standard cells at specific locations in an integrated circuit layout pattern. After generating this layout pattern, software tools, called routers, determine the physical locations of conducting paths between the cells. A number of algorithms have been developed and implemented to facilitate the automatic routing of interconnections among the circuit elements of cell-based circuit designs. These algorithms comprise the heart of the router software tools. Along with other parameters, these router algorithms use the net list parameters and attempt to automatically route the interconnections among the circuit elements of the standard cells, including the function block cells.
Most routing tools used for cell-based designs begin with the placement of circuit elements, such as standard cells and function blocks. The placement of circuit elements can be automatic, as in the case of a floor planner mentioned above, or placement can be manual. Placement of circuit elements is driven by a number of parameters, such as orientation requirements, cell placement needs relative to other dependent cells, circuit compaction requirements, and the number of interconnect lines between cells.
After placement, a typical next step for routing is commonly referred to as global routing. The global router attempts to logically determine general paths, or channels, for groups of interconnections. The global router considers many factors in determining the channels, such as available avenues for the interconnections and lengths of the interconnections. Once the global router has assigned the general flow of interconnect lines, designers use a detailed router, such as a channel router, to make the actual interconnect lines fit the assignments made by the global router. In other words, once the global assignments have been made, it becomes the job of the channel router to figure out how to route all of the lines through each channel as assigned by the global router. In simplistic terms, the channel router chooses a target from one cell and determines a particular physical path to a target on a second cell. The router repeats this process for all the defined interconnections.
To facilitate efficient routing, standard cells often have numerous cell targets for the router. Having numerous targets on the standard cells allows the router more flexibility in choosing an interconnect line destination. Put another way, the router may choose from a variety of targets to shorten interconnect lines, conform to standard cell requirements, or comply with channel restrictions. In routing the actual interconnect lines, the channel router may need to relocate the previously placed cells to implement the design. By way of example, the number of interconnect lines that must run in a certain channel may physically exceed the allotted channel width, requiring that cells be moved to increase the channel width and accommodate the interconnect lines.
Once the standard cells have been placed and routed, the net list, the cell layout definitions, the placement data, and the routing data together form an integrated circuit layout definition that is used to fabricate the integrated circuit. The integrated circuit is fabricated by depositing multiple layers on a substrate known as a wafer. The lowest “base” layers include the active areas of the transistors, including the diffusion regions, the gate oxide areas, and the desired patterns of the polycrystalline silicon gate electrodes, often referred to as polysilicon gate electrodes.
The integrated circuit layers are fabricated through a sequence of pattern definition steps that are mixed with other process steps such as oxidation, etching, doping, and material deposition. One or more metal layers are then deposited on top of the base layers to form conductive segments that interconnect the standard cells. Formation of the metallization layers over the substrate facilitates interconnection of the transistors to form more complex devices such as NAND gates, inverters, and the like. Current integrated circuits typically have six to ten metallization layers.
The metallization layers utilize lines, contacts, and vias to interconnect the transistors in each of the cells as well as to interconnect the cells to form the integrated circuit such as a processor, state machine, or memory. Lines typically reside in parallel paths within each layer. Lines in vertically adjacent layers often run perpendicular to one another, separated by a non-conductive passivation layer also referred to as an inter-level dielectric layer such as, e.g., silicon oxide. The silicon oxide is etched to form the vias, which interconnect the lines of various metallization layers in accordance with the circuit design. Inputs and outputs of the integrated circuit are brought to a surface with contacts and vias to bond the circuits with pins of a chip package. The chip package typically includes an epoxy or ceramic that encloses the integrated circuit to protect the circuit from damage and pins to facilitate a connection between the inputs and outputs of the integrated circuit and, e.g., a printed circuit board.
Using the aforementioned manufacturing process, integrated circuits have been scaled down to increase both functionality and speed available in chip packages. Designers have continually scaled down cell structures to smaller and smaller dimensions, increasing the density of cells per unit area of the substrate. Unfortunately, as cell structures and interconnect lines have shrunk, this miniaturization has brought certain manufacturing challenges.
Engineers and designers have encountered numerous manufacturing problems during the integrated circuit miniaturization process. As an example of one manufacturing problem, the interconnect lines, or wires, are sometimes placed so close that they tend to short together when created. Aside from the manufacturing problems associated with shorting wires, improperly etched via holes sometimes prevent the via from fully contacting the top and bottom metal layers. Additionally, corner rounding of polysilicon or active diffusion during the manufacturing process alters the effective dimensions of cell components, such as transistors. Because of problems such as these, design for manufacturability (DFM) techniques, such as those techniques that solve the problems of shorted wires or improperly etched via holes, have become increasingly important.
Unfortunately, DFM techniques at the cell level are not sufficient, as they only improve features internal to the cell. Improving cell external features, namely those features that may interact with other cells or the top level interconnect, must occur once the cell has been placed, or is in-situ. Because of the great number of ways the cells may be situated, it is infeasible to design an exhaustive set of layouts for each cell situation.
Instead of using DFM techniques at the cell level, designers alternatively turn to software approaches. Using software, some designers alter the top level and add additional shapes to it. However, using software to add shapes in this manner has many disadvantages. First, adding shapes to the top level significantly increases the complexity of the design. Second, designers have little control over the design, other than changing such things as the Boolean operations. Lastly, using software in this manner generally only adds shapes and complicates the design, instead of taking them away and simplifying it.
Hierarchical methods that reduce the complexity of the top level, such as reducing the number of routing target connections, have been proposed. However, such methods have limited effectiveness in reducing cell and top level complexity, due to the different situations in which a cell may be placed. For example, consider a cell that may have three DFM improvements made. Suppose further that the cell may be used in two different situations, or instances. The only DFM improvements that may be made are those that are common to both cell situations. Often, this will only allow one DFM improvement, of the three potential improvements, to be made to both cell instances.
What is needed is a new method for increasing the manufacturing reliability, or new DFM techniques, of integrated circuits at the base cell level. New DFM techniques, such as those for preventing the shorting of wires and improving vias and contacts, are needed. Additionally, these new DFM techniques should facilitate further miniaturization of integrated circuits.